Integrated circuits that include MOS transistors are particularly susceptible to damage by electrostatic discharge (ESD) events, e.g. when the circuit is touched by a person handling the circuit causing static electricity to discharge from the handler through the circuit. This is particularly the case once the circuit has been packaged but prior to it being installed in a product.
In the case of high frequency, high voltage devices such as switching voltage regulators, the design of ESD protection circuits is particularly challenging due to the overlap of the ESD regime with the normal operation regime thereby resulting in a negative ESD protection window in the voltage and time domains. In other words neither the high voltage of an ESD event nor the short dV/dt characteristics can be used to distinguish over the switching characteristics experienced by switching voltage regulators during normal operation.
Thus the prior art approach of triggering a DSCR by means of a Zener diode connected to the gate of the DSCR does not work. Although the Zener breaks down to provide the desired gate voltage to the DSCR during ESD events it will be appreciated that in high voltage applications where the normal operating voltage waveform exceeds the Zener breakdown voltage the DSCR would be triggered even during normal operation.
The present invention seeks to provide an ESD protection solution for these situations that avoids the above problems by providing an ESD protection structure with a higher breakdown voltage than the normal operating voltage of the circuit it is protecting.